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semiconductor group the hyb 314171bj/bjl is a 4 mbit dynamic ram organized as 262 144 words by 16-bit. the hyb 314171bj/bjl utilizes cmos silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. multiplexed address inputs permit the hyb 314171bj/bjl to be packed in a standard plastic 400mil wide p-soj-40-1 package. this package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. system oriented features include self refresh (l-version), single + 3.3 v ( 0.3 v) power supply, direct interfacing with high performance logic device families. 3.3v 256 k x 16-bit dynamic ram 3.3v low power 256 k x 16-bit dynamic ram with self refresh ? 262 144 words by 16-bit organization ? 0 to 70 c operating temperature ? fast access and cycle time ? ras access time: 50 ns (-50 version) 60 ns (-60 version) 70 ns (-70 version) ? cas access time: 15ns (-50,-60 version) 20 ns (-70 version) ? cycle time: 95 ns (-50 version) 110 ns (-60 version) 130 ns (-70 version) ? fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) ? single +3.3v ( 0.3 v) supply with a built- in vbb generator ? low power dissipation max. 450 mw active (-50 version) max. 378 mw active (-60 version) max. 306 mw active (-70 version) ? standby power dissipation 7.2 mw standby (ttl) 3.6 mw max. standby (cmos) 0.72 mw max. standby (cmos) for low power version ? output unlatched at cycle end allows two- dimensional chip selection ? read, write, read-modify write, cas- before- ras refresh, ras -only refresh, hidden-refresh and fast page mode capability ? 2 cas / 1 we control ? self refresh (l-version) ? all inputs and outputs ttl-compatible ? 512 refresh cycles / 16 ms ? 512 refresh cycles / 128 ms low power version only ? plastic packages: p-soj-40-1 400mil width 1 3.98 hyb 314171bj-50/-60/-70 hyb 314171bjl-50/-60/-70
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 2 ordering information truth table pin names type ordering code package description hyb 314171bj-50 p-soj-40-1 3.3v 50ns 256 k x 16 dram hyb 314171bj-60 p-soj-40-1 3.3v 60 ns 256 k x 16 dram hyb 314171bj-70 p-soj-40-1 3.3v 70 ns 256 k x 16 dram hyb 314171bjl-50 p-soj-40-1 3.3v 50 ns 256 k x 16 dram hyb 314171bjl-60 p-soj-40-1 3.3v 60 ns 256 k x 16 dram hyb 314171bjl-70 p-soj-40-1 3.3v 70 ns 256 k x 16 dram ras lcas ucas we oe i/o1-i/o8 i/o9-i/o16 operation h l l l l l l l l h h l h l l h l l h h h l l h l l l h h h h h l l l h h h l l l h h h h high-z high-z dout high-z dout din don't care din high-z high-z high-z high-z dout dout don't care din din high-z standby refresh lower byte read upper byte read word read lower byte write upper byte write word write a0-a8 address inputs ras row address strobe ucas , lcas column address strobe we read/write input oe output enable i/o1 ? i/o16 data input/output v cc power supply (+ 3.3 v) v ss ground (0 v) n.c. no connection
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 3 pin configuration p-soj-40-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vcc i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 n.c. n.c. we ras n.c. a0 a1 a2 a3 vcc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 vss i/o16 i/o15 i/o14 i/o13 vss i/o12 i/o11 i/o10 i/o9 n.c. lcas ucas oe a8 a7 a6 a5 a4 vss 22 21
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 4 block diagram no. 2 clock generator column address buffer(9) refresh controller refresh counter (9) address buffers(9) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 512 x 512 x 16 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 we ucas 512 512 x16 . ras 9 9 16 i/o1 i /o2 oe 9 9 vcc vss 16 16 9 i /o16 lcas . substrate bias generator
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 5 absolute maximum ratings operating temperature range ......................................................................................... 0 to + 70 c storage temperature range ...................................................................................... ? 55 to + 150 c input/output voltage ...................................................................................... ? 1 to (vcc+0.5, 4.6) v power supply voltage ................................................................................................... ? 1 to +4.6 v data out current (short circuit) ................................................................................................ 50 ma note: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics lv t a = 0 to 70 c; v ss = 0 v; v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit notes min. max. input high voltage v i h 2.0 vcc+0.5 v 1 input low voltage v i l ? 1.0 0.8 v 1 lvttl output high voltage ( i out = ? 2.0 ma) v oh 2.4 ? v 1 lvttl output low voltage ( i out = 2 ma) v ol ? 0.4 v 1 input leakage current, any input (0 v < v i n < vcc+0.3 v, all other inputs = 0 v) i i (l) ? 10 10 m a 1 output leakage current (do is disabled, 0 v < v out < v cc + 0.3 v ) i o(l) ? 10 10 m a 1 average v cc supply current: -50 version -60 version -70 version i cc1 125 105 85 ma 2, 3, 4 standby v cc supply current ( ras = lcas = ucas = we = v i h ) i cc2 2 ma average v cc supply current during ras -only refresh cycles: -50 version -60 version -70 version i cc3 125 105 85 ma 2, 4
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 6 dc characteristics (cont?d) capacitance t a = 0 to 70 c; v cc = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit notes min. max. average v cc supply current during fast page mode operation : -50 version -60 version -70 version i cc4 70 65 60 ma 2, 3, 4 standby v cc supply current ( ras = l cas = ucas = we = v cc ? 0.2 v) i cc5 1 ma 1 average v cc supply current during cas -before- ras refresh mode: -50 version -60 version -70 version i cc6 125 105 85 ma 2, 4 standby v cc current (l-version) ( ras = lcas = ucas = we = v cc ?0.2 v) i cc5 200 m a self refresh current (l-version) ( ras , lcas , ucas = 0.2v a0?a8= v cc ? 0.2v or 0.2v) i ccs 250 m a parameter symbol limit values unit min. max. input capacitance (a0 to a8) c i 1 ? 6 pf input capacitance ( ras , ucas , lcas , we , oe ) c i 2 ? 7 pf output capacitance (l/o1 to l/o16) c i o ? 7 pf
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 7 ac characteristics 5)6) t a = 0 to 70 c; v ss = 0 v; v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit note - 50 - 60 - 70 min. max. min. max. min. max. common parameters random read or write cycle time t rc 95 ? 110 ? 130 ? ns ras precharge time t rp 35 ? 40 ? 50 ? ns ras pulse width t ras 50 10k 60 10k 70 10k ns cas pulse width t cas 15 10k 15 10k 20 10k ns row address setup time t asr 0 ? 0 ? 0 ? ns row address hold time t rah 10 ? 10 ? 10 ? ns column address setup time t asc 0 ? 0 ? 0 ? ns column address hold time t cah 10 ? 15 ? 15 ? ns ras to cas delay time t rcd 20 35 20 45 20 50 ns ras to column address delay time t rad 15 25 15 30 15 35 ns ras hold time t rsh 15 ? 15 ? 20 ? ns cas hold time t csh 50 ? 60 ? 70 ? ns cas to ras precharge time t crp 5 ? 5 ? 5 ? ns transition time (rise and fall) t t 3 50 3 50 3 50 ns 7 refresh period t ref ? 16 ? 16 ? 16 ms refresh period (l-version) t ref ? 128 ? 128 ? 128 ms read cycle access time from ras t rac ? 50 ? 60 ? 70 ns 8, 9 access time from cas t cac ? 15 ? 15 ? 20 ns 8, 9 access time from column address t aa ? 25 ? 30 ? 35 ns 8,10 oe access time t oea ? 15 ? 15 ? 20 ns column address to ras lead time t ral 25 ? 30 ? 35 ? ns read command setup time t rcs 0 ? 0 ? 0 ? ns read command hold time t rch 0 ? 0 ? 0 ? ns 11 read command hold time ref. to ras t rrh 0 ? 0 ? 0 ? ns 11 cas to output inlow-z t clz 0 ? 0 ? 0 ? ns 8
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 8 output buffer turn-off delay from cas t off 0 15 0 20 0 20 ns 12 output buffer turn-off delay from oe t oez 0 15 0 20 0 20 ns 12 data to oe low delay t dzo 0 ? 0 ? 0 ? ns 13 cas high to datadelay t cdd 15 ? 20 ? 20 ? ns 14 oe high to data delay t odd 15 - 20 ? 20 ? ns 14 write cycle write command hold time t wch 10 ? 10 ? 15 ? ns write command pulse width t wp 10 ? 10 ? 15 ? ns write command setup time t wcs 0 ? 0 ? 0 ? ns 15 write command to ras lead time t rwl 15 ? 15 ? 20 ? ns write command to cas lead time t cwl 15 ? 15 ? 20 ? ns data setup time t ds 0 ? 0 ? 0 ? ns 16 data hold time t dh 10 ? 15 ? 15 ? ns 16 data to cas lowdelay t dzc 0 ? 0 ? 0 ? ns 13 read-modify-write cycle read-write cycle time t rwc 140 ? 160 ? 185 ? ns ras to we delay time t rwd 75 ? 90 ? 100 ? ns 15 cas to we delay time t cwd 40 ? 45 ? 50 ? ns 15 column address to we delay time t awd 50 ? 60 ? 65 ? ns 15 oe command hold time t oeh 15 ? 20 ? 20 ? ns fast page mode cycle fast page mode cycle time t pc 35 ? 40 ? 45 ? ns cas precharge time t cp 10 ? 10 ? 10 ? ns access time from cas precharge t cpa ? 30 ? 35 ? 40 ns 7 ras pulse width t rasp 50 200k 60 200k 70 200k ns ras hold time from cas precharge t rhcp 30 ? 35 ? 40 ? ns parameter symbol limit values unit note - 50 - 60 - 70 min. max. min. max. min. max.
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 9 fast page mode read modify write cycle fast page mode read/write cycle time t prwc 80 ? 90 ? 100 ? ns cas precharge to we delay time t cpwd 55 ? 60 ? 65 ? ns cas before ras refresh cycle cas setup time t csr 5 ? 5 ? 5 ? ns cas hold tim t chr 10 ? 10 ? 10 ? ns ras to cas precharge time t rpc 0 ? 0 ? 0 ? ns write to ras precharge time t wrp 10 ? 10 ? 10 ? ns write to ras hold time t wrh 10 ? 10 ? 10 ? ns cas -before ras counter test cycle cas precharge time t cpt 25 ? 30 ? 40 ? ns self refresh cycle (l-version only) ras pulse width t rass 100 ? 100 ? 100 ? m s ras precharge time t rps 95 ? 110 ? 130 ? ns cas hold time self refresh t chs 35 ? 40 ? 50 ? ns parameter symbol limit values unit note - 50 - 60 - 70 min. max. min. max. min. max.
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 10 notes: 1) all voltages are referenced to v ss . 2) i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3) i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 4) address can be changed once or less while ras = vil. in case of icc4 it can be changed once or less during a page mode cycle 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas -before- ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume t t = 5 ns. 7) v i h (min.) and v i l (max.) are reference levels for measuring timing of input signals. transition times are also measured between v i h and v i l . 8) measured with a load equivalent to 100 pf and at voh=2.0v (ioh=-2ma), vol=0.8v (iol=2ma). 9) operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10) operation within the t rad (max. ) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11) either t rch or t rrh must be satisfied for a read cycle. 12) t off (max.) , t oez (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 13) either t dzc or t dzo must be satisfied. 43) either t cdd or t odd must be satisfied. 15) t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) and t awd > t awd (min.) , the cycle is a read-write cycle and i/o will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 16) these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles.
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 11 read cycle row column row valid data out ras ucas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z ?h? or ?l? wl1 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 12 write cycle (early write) ras ucas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column row row t rah t wcs ?h? or ?l? wl2 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 13 write cycle ( oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row t dzc ?h? or ?l? hi-z hi-z column row t asc t rad t ral t cah t rah ras ucas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr wl3 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 14 read-write (read-modify-write) cycle row row t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il t asr column t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac ?h? or ?l? t asc v ih v il v ih v il ras ucas address v ih v il wl4 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 15 fast page mode read cycle t rasp t cas t cas t pc t cp t rcd t csh t cah t cah t asc t asc t asr t rah t rad t rcs t rcs t rcs t asc t cah t cas t rsh t crp t rp t asr t rch t cpa t oea t oea t aa t aa t dzc t dzc t cdd t rrh t cpa t oea t aa t dzc t dzo t odd t odd t dzo t odd t dzo t off t oez t oez t off t oez t cac t cac t clz t clz t clz t off t rac t cac valid data out data out data out valid valid column column row row ras i/o (outputs) i/o (inputs) oe we address ucas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ?h? or ?l? t rhcp t rch v oh v ol column fpm1 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 16 fast page mode early write cycle t ras t rp t rsh t cas t cas t cp t crp t ral t cah t asr t cwl t rwl t cah t asc t asc t cwl t cwl t wcs t wcs t wcs t wch t wp t wp t wch t wp t wch t rad t cas t rcd t pc t cah t rah t asr t asc t dh t ds t ds t dh t dh t ds column column column row valid data in valid valid data in data in column hi-z ras i/o (outputs) i/o (inputs) oe we address ucas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ?h? or ?l? v oh v ol fpm2 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 17 fast page mode read-modify-write cycle t c a h t c p t d z c t d z o t r a c t c a c t c l z t r c s t a a t o e a t r c d t r a d t r a h t a s r t a s c t c a s t c a s t p r w c t c w d t c a h t a s c t c a s t r s h t r p t c r p t a s r t c a h t a s c t r a l t c w d t r w d t c w l t c w l t c w d t a w d t a w d t w p t w p t c w l t r w l t a w d t w p t o d d t o e h t d h t d s t c p a t o e z t c l z t d z c t a a t c a c t o e a t d s t o e z t d h t o e h t a a t o d d t d z c t c p a t o e a t c l z t d s t d h t o e h t o d d r a s v i h v i l u c a s v i h v i l v i h v i l v i h v i l v i h v i l v i h v i l v o h v o l w e o e a d d r e s s i / o ( i n p u t s ) i / o ( o u t p u t s ) d a t a i n d a t a i n d a t a i n d a t a o u t o u t d a t a d a t a o u t r o w c o l u m n a d d r e s s c o l u m n r o w t r a s t c s h c o l u m n t c p w d t c p w d ? h ? o r ? l ? t o e z l c a s
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 18 ras -only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row row hi-z address ras ucas i/o (outputs) ?h? or ?l? wl9 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 19 cas -before- ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z ?h? or ?l? ras i/o (outputs) i/o (inputs) oe we ucas v oh v ol wl10 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 20 cas before ras self refresh cycle t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z ?h? or ?l? ras i/o (outputs) i/o (inputs) oe we ucas v oh v ol t chs wl13 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 21 hidden refresh cycle (read) ras i/o (outputs) i/o (inputs) oe we address ucas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh ?h? or ?l? valid data out row column row hi-z v oh v ol wl11 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 22 hidden refresh cycle (early write) ras i/o (output) i/o (input) we address v ih v il v ih v il v ih v il ucas v ih v il v ih v il ?h? or ?l? t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc row row valid data hi-z column v oh v ol t wrp t wrh wl12 lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 23 cas/ -before- ras refresh counter test cycle t csr t asr t asc t chr t cp t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t dh v ih v il v ih v il v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras i/o (inputs) oe we address ucas i/o (outputs) i/o (outputs) i/o (inputs) we oe column row data out data in hi-z read cycle: write cycle: t rrh t rch lcas
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 24 package outline 1) does not include plastic or metal protrusions of 0.25 max per side index marking gpj09018(w) plastic package, p-soj- 40-1 (smd) (plastic small outline j-lead) dimensions in mm
hyb314171bj/bjl-50/-60/-70 3.3v 256 k x 16-dram semiconductor group 25 revision changes: rev. 3.98 cmos output levels removed

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